| 摘要 |
PURPOSE:To prepare a program without being conscious of the timing of a pipeline by suppressing the output of a register until the execution result of a preceding instruction is obtained and holding the contents of an instruction register and a counter. CONSTITUTION:Simultaneously when an instruction A is executed, an instruction B is fetched into an instruction register 103. A first decoder 105 outputs '1' to the instruction B, which is a conditional branching instruction, so that the execution of the instruction B can be started from when the execution result of the instruction A can be decided (namely, up to one cycle before in which the execution of the preceding instruction A is completed) and a selector 106 selects a non-execution instruction. When the execution result of the preceding instruction A can be decided, the decoder 105 outputs '0', the instruction B fetched into the instruction register 103 is decoded by a decoder 107 and thereafter, the instruction is executed by an executing unit 108.
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