发明名称 ADDER
摘要 PURPOSE:To curtail the quantity of a hardware and to attain a high speed by executing the substantial part of an addition only in a column in which an augend and an addend are present and adding a carry after a next step. CONSTITUTION:A first means for executing an intermediate addition in which the augend and the addend are present, a second means for saving the addition in a part in which one number, namely either the augend or the addend is present and making the other number namely, the addend or the augend directly a sum, a third means for storing the carry generated according to the addition of the first means and adding in the addition after the next step and a fourth means for directly outputting externally a part in which one low order number, namely, only the augend or the addend is present from a part in which the columns are overlapped are provided. To the addition of numbers except a number in which the most significant column of the respective steps of an addition tree is situated at the lowest order and a number in which it is situated in the order next to the lowest order, the addition of the two numbers is simultaneously executed by the first - the third means to obtain the sum. Thereby, the quantity of the hardware is curtailed and the high speed is attained.
申请公布号 JPS63298525(A) 申请公布日期 1988.12.06
申请号 JP19870135069 申请日期 1987.05.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKAGI TADASHI;HATSUDA TSUGUYASU;TANIGUCHI TAKASHI
分类号 G06F7/49;G06F7/50;G06F7/505;G06F7/52;G06F7/53 主分类号 G06F7/49
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