| 摘要 |
PURPOSE:To prevent the data missing of a data bit without affecting on the corresponding bit of inputted data from occurring, by performing memory development by latching already written data with an input data fetching timing, and overlapping it on input data when the input data is written on a RAM. CONSTITUTION:A shift value is latched at latch circuits 8 and 29 from a CPU based on a shift quantity instruction signal 18. Next, the CPU outputs an address and data to an address bus 19 and a data bus 10, respectively. A bit shift circuit 9 outputs the data of a first byte shifted corresponding to the shift quantity instruction signal 18 to a latch circuit 11 and an OR circuit 12 as shift data 14. A timing generation circuit 1 sets a read/write signal at LOW, and informs a completion signal 17 to the CPU after writing the input data on the RAM4. And the bit shift circuit 9 latches the bit shift data 14 of a second byte at the latch circuit 11.
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