Via in a planarized dielectric and process for producing same

摘要

An improved integrated circuit structure is disclosed wherein a first metal layer is coated with a dielectric material and another metal layer is applied over the dielectric layer and a via electrically interconnects at least a portion of the first metal layer with at least a portion of the second metal layer. The via is formed having a lower first width dimension adjacent the first metal layer and an upper enlarged width portion adjacent the second metal layer formed by masking the dielectric with a mask having an opening conforming to the first dimension and isotropically etching the dielectric through the mask to provide the enlarged portion adjacent the upper surface of the dielectric.