| 摘要 |
PURPOSE:To eliminate the need for a selector bus line by providing a means to apply parity check to each output of a split horizontal group selector and a split vertical group selector. CONSTITUTION:Cell information sets C2, C6, C14, P2 belonging to the same horizontal group as the memory cell information C10 are selected by a split horizontal group selector 10 by selection signals, the -A1A0 and the result is sent to nodes N12-N16. On the other hand, similarly cell information sets C4, C7, C13, P8 belonging to the same vertical group as the memory cell information C10 are selected by a split vertical group selector 11 by selection signal A3A2 outputs and the result is sent to nodes N17-N21. Then the horizontal group parity check and vertical group parity check are applied similarly in a cascade connection circuit of one input parity circuit 8 and the data of the node N25 of the output of a multiplexer 7 is corrected by the combination and the result is fed to an output terminal. Thus, no selector use bus line is required.
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