发明名称 HARDWARE MODELING SYSTEM AND METHOD FOR SIMULATING PORTIONS OF ELECTRICAL CIRCUITS
摘要 <p>HARDWARE MODELING SYSTEM AND METHOD FOR SIMULATING PORTIONS OF ELECTRICAL CIRCUITS A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user's vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.</p>
申请公布号 CA1246222(A) 申请公布日期 1988.12.06
申请号 CA19860503049 申请日期 1986.02.28
申请人 MENTOR GRAPHICS CORPORATION 发明人 BECK, RONALD R.;STANBRO, MICHAEL E.;THOMSEN, ERIC J.
分类号 G06F17/50;(IPC1-7):G06F15/60 主分类号 G06F17/50
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