发明名称 BIT SCAN CIRCUIT
摘要 PURPOSE:To attain high speed by applying the clock of a frequency of the multiple of integer of the operating clock of an arithmetic circuit to one bit shift register and executing one bit shift operation with plural number of times within a time in which an ordinary operation is executed by the arithmetic circuit. CONSTITUTION:The titled circuit is provided with a arithmetic circuit 1 arithmetically operated by the operating clock, a shift register 2 for executing the shift operation by the clock with the multiple of integer of the operating clock of this arithmetic circuit 1, and a shift number counting circuit 3 initialized according to an instruction from the arithmetic circuit 1. Accordingly, the inspection of data to be scanned to the one bit can be executed with the plural number of times within the time of one clock of the operating clock of the arithmetic circuit 1. Thereby, it seems that the bit scanning operation is carried out at high speed from the arithmetic circuit 1.
申请公布号 JPS63298521(A) 申请公布日期 1988.12.06
申请号 JP19870133806 申请日期 1987.05.29
申请人 NEC CORP 发明人 YAMAZAKI ATSUSHI
分类号 G06F7/00;G06F7/74 主分类号 G06F7/00
代理机构 代理人
主权项
地址