发明名称 SEQUENTIAL DECODER
摘要 PURPOSE:To improve the transmission efficiency of a line, by providing a coding ratio conversion circuit which converts a code to a organization code with a low coding ratio by adding a dummy parity bit on a received signal and also generates a signal which prohibits Fanometric arithmetic operation, and selecting the coding ratio of an error correction code corresponding to the quality of the line. CONSTITUTION:It is advisable that the number of parity bits is increased to convert the organization code with a large coding ratio, for example, whose coding ratio is 3/4 to the one with the low coding ratio. To realize that, the number of the parity bits is increased by adding the dummy parity bit by the coding ratio conversion circuit, and it is converted to the organization code with the low coding ratio. When such dummy parity bit is added, a fanometric arithmetic operation prohibiting signal for reception data is supplied from the coding ratio conversion circuit 21 to a sequential decoder 22. Then, the coding ratio is varied by switching the generator matrix of the organization code and the conversion table of a fanometric conversion circuit based on a coding ratio switching signal.
申请公布号 JPS63299412(A) 申请公布日期 1988.12.06
申请号 JP19870131240 申请日期 1987.05.29
申请人 FUJITSU LTD 发明人 SHIMODA KANEYASU;AGENO YUUZOU
分类号 H03M13/23 主分类号 H03M13/23
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