发明名称 DELAY ANALYSIS SYSTEM
摘要 PURPOSE:To shorten the processing time required for delay analysis by correcting a delay network model and performing the delay analysis of only propagation routes to which a design changed partial network is related. CONSTITUTION:A delay network model generated in accordance with delay network model generating procedures or a delay network model obtained by correcting said generated delay network model in accordance with delay network model correcting procedures is read out from a delay network model file 5a. The propagation delay time of each of propagation routes to which the partial network designated by a user is related or all propagation routes of a network is calculated and is recorded in a propagation delay time file 7a. Contents of the propagation delay time file 7a are read out to discriminate whether the propagation delay time of each propagation delay route calculated in accordance with bus trace procedures is in an allowable range of the propagation delay time inputted and designated by the user or not, and the propagation delay time of each propagation route is displayed on a CRT display device or is outputted to an output device like a printer if it exceeds the allowable range.
申请公布号 JPS63296173(A) 申请公布日期 1988.12.02
申请号 JP19870132178 申请日期 1987.05.27
申请人 NEC CORP 发明人 HYODO NORIAKI
分类号 G06F11/26;G06F17/50 主分类号 G06F11/26
代理机构 代理人
主权项
地址