发明名称 SETTLING TIME REDUCTION CIRCUIT FOR FILTER
摘要 PURPOSE:To attain steep change in a generated DC voltage together with the reduction in the settling time of a filter by connecting a means generating nearly equal DC voltage to a DC component of an input signal to an AC ground terminal. CONSTITUTION:A terminal 14 of a low-pass filter 6 is not connected to ground but connected to a point having a voltage Vapprox close always to an output voltage Vout. Even when a DC voltage has a change at an input terminal 16, it is not required to charge or discharge various capacitors of the filters com pletely. Thus, the capacitors have only to be charged again for the difference in value between terminals 16 and 14 and the difference can be made very slight and easily attained with respect to the Vout. Thus, the value of time constant required to reach a desired setting time is very small.
申请公布号 JPS63296406(A) 申请公布日期 1988.12.02
申请号 JP19880107507 申请日期 1988.04.28
申请人 YOKOGAWA HEWLETT PACKARD LTD 发明人 SUTEIIBUN JIEI NARUKITSUSO
分类号 H03M1/08;H03H11/12 主分类号 H03M1/08
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