| 摘要 |
PURPOSE:To reduce parasitic capacitances and increase the operation speed of a semiconductor device by a method wherein a current applied between 1st and 3rd impurity regions is controlled by a voltage applied to a control electrode formed on the side of a 2nd impurity region with an insulating film between. CONSTITUTION:A pillar-shape structure composed of a source region 1, a P-type impurity region 2 and a drain region 3 is formed inside a gate electrode 5 with a silicon oxide film 4 between. The gate electrode 5 is so formed as to surround the side of the P-type impurity region 2 with the silicon oxide film 4 between. With this constitution, P-N junctions between the source and drain regions 1 and 3 which are N-type impurity regions and the P-type impurity region 2 exist only inside the gate electrode 5 with the silicon oxide film 4 between so that the capacitances of the P-N junctions parasitizing the source region 1 and the drain region 3 can be reduced and, as the gate width of the gate electrode 5 is enlarged, the operation speed of the device can be increased.
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