| 摘要 |
PURPOSE:To decrease a circuit scale by sampling a C-bit and a bit just before, using a signal obtained as the result to convert the mBIC code rule into a low speed alternate rule, then supervising the alternate rule. CONSTITUTION:Means 2, 3 sampling a C-bit of mBIC (m Binary with 1 Complement Insertion) digital signal and a bit just before, means 4, 5 using a signal obtained the result of sampling by the means 2, 3 to convert the mBIC code rule into a low speed '1', '0' alternate rule, and means 6, 7 applying error detection of the '1', '0' alternate rule obtained by the means 4, 5 are provided. That is, the C bit and the bit just before are sampled, the signal obtained as the result is used to convert the mBIC code rule into a low speed '1', '0' alternate rule, then the alternate rule is supervised to detect the C bit error. Since the circuit consists of conventional OR gates and NOR gates only, the cost of the entire device is reduced and the circuit scale is decreased.
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