A parity-checking semiconductor circuit for a data transfer device having parity-checking of the pulse count of a digital signal comprises an exclusive OR (1), to which digital communication data are given as first input, and a latch circuit (30) to which the output signals of the exclusive OR circuit (1) are input and whose output signals are input to the exclusive OR circuit (1) as second input, so that the digital communication data are input sequentially to the exclusive OR circuit (1) and the parity-checking of the pulse count of the digital signal is carried out, by which means the parity-checking of the pulse count of the digital signal can be carried out simultaneously with the input/output of the digital communication data. <IMAGE>
