| 摘要 |
The adder circuit according to the subject of the invention differs from the adder circuit according to P 3714665.3 mainly in that the main circuit 2 processes the value 2, not the value 1. Thus, in this adder circuit, a dual full adder 6 is also required to process the value 1, because the derived partial summands with the value 1 must be processed or pre-processed in a dual full adder. If a 1 or three 1s are present, output m of the dual full adder 6 has high potential, and this 1 is processed in the one upwards shift circuit 4, which is combined with a straight-through circuit. <IMAGE>
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