| 摘要 |
A processor control system having a plurality of memories (5, 6, 7). A microprocessor (1) is provided with an ordinary address bus (2), a data bus (3), and a dedicated instruction read bus (4) connected with an instruction memory (5). Since the instruction read bus (4) is provided, the processor (1) executes the instruction while reading the instruction from the instruction read bus (4). Therefore, the processor (1) can operate at an increased speed. |
