| 摘要 |
PURPOSE:To lower offset voltage generated between output terminals for a Hall element by electrically connecting the positive pole of an input terminal for one Hall element and the positive pole of an input terminal for the other Hall element so that the positive pole of the input terminal for one Hall element is used as an input terminal in the direction tying a pair of input terminals on a semiconductor wafer and the positive pole of the input terminal for the other Hall element is employed as an input terminal formed on another end side. CONSTITUTION:Arbitrary two of a plurality of Hall elements H1, H2, H3... shaped so that AB axes tying pairs of input terminals 3a, 3b on a wafer 1 are made mutually parallel are paired, and the Hall elements are connected electrically so that the positive pole of one Hall element H1 is used as the input terminal 3a shaped on the end A of the axis AB and the positive pole of the other Hall element H2 is employed as the input terminal 3b formed on the end B of the axis AB. Accordingly, even when each output terminal 4a, 4b for the Hall elements H1, H2, H3... is formed to a geometrically asymmetric shape by reason of the shortage, etc., of the accuracy of mask alignment and photosensitive accuracy, the offset voltage VHO of one Hall element H1 and the offset voltage VHO of the other Hall element H2 are offset, thus acquiring the Hall elements having low offset voltage VHO.
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