| 摘要 |
PURPOSE:To output a clock signal with a constant duty decided by a delay circuit, by delaying the output signal of a D.FF which performs the two- frequency division of the clock signal for a constant time at the delay circuit, and taking OR by inputting the output signal of the D.FF and that of the delay circuit. CONSTITUTION:The titled circuit is constituted of the D.FF which two-frequency divides the clock signal, the delay circuit 2 which inputs the output signal of the FF and outputs the same signal after delaying the output signal for the constant time, and an OR circuit 3 which inputs the output signal of the FF and that of the delay circuit and takes the OR of them. And the D.FF1 outputs a signal 12 when a signal 11 is inputted. The delay circuit 2 outputs the signal based on a delay time set at the delay circuit 2 when the signal 12 is inputted. The OR circuit 3 outputs a signal 14 when the signals 12 and 13 are inputted. In such a way, it is possible to reproduce the clock with the constant duty set at the delay circuit 2 in spite of the change of an inputted clock signal.
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