| 摘要 |
PURPOSE:To improve the following property of a digital PLL circuit, by generating correction controlling pulses in a basic period time following a basic period during which input digital signals are generated and controlling the frequency dividing ratio of a counter in this time only and, at the same time, combining DC correcting signals corresponding to a DC component with the output signal of a digital low-pass filter. CONSTITUTION:A correction controlling pulse generating circuit 14 which generates correction controlling pulses in a basic period time following a basic period during which input digital signals are generated is provided and the output signal of a digital low-pass filter 12 is supplied to a counter 13 only in the correction controlling pulse generating period. Then the DC component of the input digital signals is detected and DC correcting signals are generated in corresponding to the detecting output and combined with the output signal of the low-pass filter 12. Therefore, errors in quantization can be reduced and the DC component of input data is corrected, resulting in improvement in following property. |
