发明名称 STEREO DEMODULATION CIRCUIT
摘要 PURPOSE:To realize the demodulation circuit with high performance, by superimposing a stereo composite signal on a prescribed reference voltage and applying the result to L, R amplifiers by switching means to prevent the increase in a distortion factor and the reduction in a dynamic range. CONSTITUTION:A 38kHz in-phase signal A is applied to each base of transistors (TRs)Q1, Q2, Q13, Q14 and a 38kHz opposite phase signal 8 is applied to each base of TRsQ3, Q4, Q11, Q12 at the stereo operation, and outputs of operational amplifiers OP2, OP1 go to respectively L, R channel signals. A high level signal C and a low level signal D are generated from a 19kHz detecting circuit 5 at the monaural signal receiving to turn on the TRsQ1, Q4, Q11, Q14 and Q2, Q3, Q12, Q14, the outputs of the amplifiers OP1, OP2 are the same and of the same level as the stereo operation. When no receiving signal exists in an IF amplifier 1 at the muting, a muting signal generating circuit 7 generates high and low level muting signals E, F to turn on/off the TRs, allowing to attain the muting.
申请公布号 JPS5977732(A) 申请公布日期 1984.05.04
申请号 JP19830161696 申请日期 1983.09.02
申请人 PIONEER KK 发明人 NUMATA TATSUO;ISHIDA KOUJI
分类号 H03D1/22;H04H40/45 主分类号 H03D1/22
代理机构 代理人
主权项
地址