| 摘要 |
PURPOSE:To easily correct the offset by decoding and displaying the contents of the BCD counter in case the binary U/D counter for controlling the dividing number of the programmable divider has conformed with the contents of the binary counter. CONSTITUTION:In case IF in FM is -10.7MHz, when the receiving frequency is 76MHz, the local oscillation frequency is 65.3MHz and the frequency dividing number of the programmable divider 14 of the PLL device is 653. It is made 654 by adding +1 at the time of rise of a clock pulse CL2 for channel selection by the binary U/D counter 10 for controlling the said dividing number. The clock pulse CL1 is counted by the offset counter 21 and the BCD counter 23, and when the counter 21 has counted the offset portion 107, the binary counter 20 starts counting, and the contents of the counter 23 in case the contents of the counters 20, 10 have conformed to each other and have been detected 19 becomes the value of the receiving frequency. Namely, the receiving frequency of 76.1MHz can be obtained by multiplying the sum 761 of 107 and 654 by the channel base 100kHz. |
