发明名称 SPEED-CHANGEABLE REPRODUCING SYSTEM
摘要 PURPOSE:To timely and certainly perform switching of readout from a memory when speed-changeable reproduction is made by utilizing a memory, by recognizing fixed address numbers. CONSTITUTION:Reproducing address signals added to image signals are set in such a way that, for example, a first address number of a field is set to '01' and the last address number is set to '11' when the field is inputted to a terminal 10. Then a reproducing address number B is inputted to an address discriminating circuit 20 and, when the inputted reproducing address number B coincides with a previously set number, for example, the first address number of a field, the address discriminating circuit 20 outputs a decision signal C. During the period from the memory to the time when the address discriminate signal C is outputted, reproduced data is written in a field memory and image signals of one field quantity are stored in the memory. Therefore, switching of the field memory can be performed certainly and accurately.
申请公布号 JPS63294191(A) 申请公布日期 1988.11.30
申请号 JP19870128189 申请日期 1987.05.27
申请人 HITACHI LTD 发明人 YAMAUCHI HIROTO
分类号 H04N5/937;H04N5/93 主分类号 H04N5/937
代理机构 代理人
主权项
地址