| 摘要 |
PURPOSE:To improve the using efficiency of a memory area and to loosen a timing condition at the time of data transfer by providing the titled device with a random access ports for inputting/outputting storage data in each prescribed number of bits through respective I/O terminals and serial access ports for serially inputting/outputting data. CONSTITUTION:Four groups of memory arrays M-ARY1-M-ARY4, the number of memory arrays is not especially restricted, are formed in a dual port memory and the random access ports and the serial access ports are connected through these memory arrays. The number of data I/O terminals of the serial access ports is set up to 1/the second power the number of data I/O terminals of the random access port and a shift register for holding storage data input/outputted through plural common data lines corresponding to respective data I/O terminals of the serial access ports is formed. Consequently, the mounting efficiency of the system can be improved and the timing condition at the time of data transfer can be loosened.
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