| 摘要 |
PURPOSE:To improve the circuit integration by arranging n-channel and p- channel MOSFETs corresponding to '0', '1' of a truth table so as to decrease the number of the MOSFETs. CONSTITUTION:A matrix array comprising MOSFETs is formed by arranging a P-channel MOSFET 31 to '0' of the truth table and an N-channel MOSFET 32 to '1' of the said table, and an address line 21, an output signal line 22 and an input signal line 23 are provided. In applying a low potential to '0' of the truth table and a high potential to '1' through address lines A1-A8, a pulse phiD of the input signal line 23 is outputted sequentially from output lines L1-L4. Thus, the number of MOSFETs is halved in comparison with that of a conventional decoder, and the number of address signal lines is halved because no inverted signal lines are required, thereby simplifying the circuit constitution of the decoder.
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