| 摘要 |
PURPOSE:To reduce the cost of a whole device, by carrying out error detection with low-speed signals in such a way that a C-bit and the bit immediately before the C-bit are respectively sampled and the exclusive OR of a low-speed C-bit string and the bit string immediately before the C-bit string obtained as the results of the samples is taken. CONSTITUTION:Error detection is carried out with low-speed signals in such a way that a C-bit and the bit immediately before the C-bit are respectively sampled and the exclusive OR of a low-speed C-bit string and the bit string immediately before the C-bit string obtained as the results of the samples is taken. Since the signal frequency for taking the exclusive OR is lower in speed than original signals, therefore, the use of an expensive logic element is eliminated. Moreover, plural logic elements (D-flip flop 1 and 2 and OR gate 4), a frequency dividing circuit 5, and a synchronous circuit 7 operate at high speeds, error detection can be performed sufficiently and, accordingly, the number of sections which require expensive logic elements can be reduced. Therefore, the cost of the whole device can be reduced.
|
