发明名称 Decision timing control circuit
摘要 A circuit is provided for controlling the decision timing of an A/D converter so that error rate becomes small. Error rate information is obtained based on the converted digital signal from the A/D converter. This information is used for controlling the phase of an A/D converter clock signal to thereby control the decision timing of the A/D converter.
申请公布号 US4788696(A) 申请公布日期 1988.11.29
申请号 US19870063479 申请日期 1987.06.18
申请人 FUJITSU LIMITED 发明人 SAKANE, TOSHIAKI;IIZUKA, NOBORU;IWAMATSU, TAKANORI
分类号 H04L27/38;H04L7/02;H04L7/04;H04L27/22;(IPC1-7):H04L7/04 主分类号 H04L27/38
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