ADDRESS GENERATING CIRCUIT FOR FAST FOURIER TRANSFORM

摘要

PURPOSE:To omit the change of a circuit despite the change of a bit width by using a shift value control information production/output circuit containing a complement production/output circuit and a bit order exchange circuit which outputs a bit reverse address in response to an address given from a barrel shifter. CONSTITUTION:A shift value information production/output circuit 1 includes a decrementer which has the input of (n) and the output of (n-1) and a complement production/output circuit 3 which has the input of (n-1) outputted from said decrementer and accordingly produces a complement '1' of (n-1) to output it as the shift value control information showing the number of bits. A barrel shifter 4 outputs an address having a mode where the zero contents are buried into an idle bit. Then a bit order exchange circuit 5 consists of wiring which has the input of an address given from the shifter 4 and has the output of a bit reverse address in response to said address. In such constitution, it is not required to change the circuit constitution in accordance with the change of the bit width.