| 摘要 |
The invention relates to an apparatus for interfacing between a peripheral device and a host processor. The invented cache memory and pre-processor operates in either an acquisition mode, where it appears to be a memory dedicated to the peripheral, or in a retrieval mode, where it appears to be a memory dedicated to the host microprocessor. For example, the cache memory can be reconfigured from a 2K byte by 16-bit space during the acquisition mode to a 4K byte x8-bit space during the retrieval mode, wherein the high and low bytes of the previously defined 16-bit words are interleaved.
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