| 摘要 |
PURPOSE:To decrease the number of the times of an access to a memory unit by executing the data transfer of a memory unit and a peripheral control unit with the data width of a bus at a memory unit side. CONSTITUTION:One port out of plural ports of a memory unit, a peripheral control unit and a direct memory access unit are connected to the bus of the data width of an (n) byte [(n) is a natural number of two or above]. A peripheral control unit 13 has the data width of an (m) byte [(m) is a natural number which is m<n], connected to a part of the bus and the direct memory access unit 12 is equipped with a data buffer 100. the transfer between a memory unit 10 and a peripheral control unit 14 is executed through the data buffer 100, an (n) byte transfer is executed between the memory unit 10 and the data buffer 100 and an (m) byte transfer is executed between the data buffer 100 and the peripheral control unit 13. Thus, the number of the times of the access to the memory unit is decreased and the data transfer control is efficiently executed. |
