| 摘要 |
PURPOSE:To improve the inter-memory transfer efficiency by providing a signal line on a common bus to control a refresh cycle and performing simultaneously the refreshing actions for dynamic RAMs of each board. CONSTITUTION:When a refresh enable signal is received via a refresh control lines set on a system bus 1, a refresh control circuit 10 set in a board delivers a refresh address to refresh a D-RAM (page memory 31 or system memory 7). Therefore the DMA cycle is delayed only when a video memory 51 is refreshed so that the DMA refreshment is carried out with extremely high efficiency. Thus the inter-memory transfer is carried out at a high speed within a system. |
