| 摘要 |
PURPOSE:To enable a latch-up phenomenon to be prevented by a method wherein a resistor, which renders a flowing current smaller than a latch-up current which is a power supply current flowing at the time when a parasitic thyristor starts to be conductive, is provided between a power supply terminal of a gate circuit and a power supply terminal of an integrated circuit device. CONSTITUTION:A CMOS integrated circuit device 1 constitutes a gate circuit 2 by combining a P channel transistor with an N channel, where a resistor 3, which renders a flowing current smaller than a latch-up hold current IH that is a power supply current flowing at the time when a parasitic thyristor starts to be conductive, is interposed between a power supply terminal 4 of the gate circuit 2 and a power supply terminal 4' of the integrated circuit device 1. For example, the resistor 3 is connected between the positive voltage power supply terminal 4 of the gate circuit 2 and the positive voltage power supply terminal 4' of the integrated circuit device 1. And, when resistance value of the resistor 3 denotes R, voltage of a power supply is represented by VDD, and the latch-up hold current of the integrated circuit device 1 is IH, resistance value of the resistor 3 should be determined so as to satisfy inequalities IH>VDD/ R, i.e., R>VDD/IH.
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