| 摘要 |
PURPOSE:To speed up operation by using an address stack with a comparing function. CONSTITUTION:An inputted fetch address FA is stored in a stack registers SR31-34 and then sent as a storing address through a selection circuit 42. An IN point register 43 specifies the stack register to store the address out of the SR 31-34. An instruction to the circuit 42 is applied by an OUT pointer register 44. Respective addresses stored in the SR31-34 are address of preceding elements to be written in a main storage, and when any one of the addresses coincides with the one indicated on an address line 14, any one of comparators 36-39 outputs a coincidence signal and an FA sending suppressing signal is transmitted by a control line 16 through an OR gate 14. At the time of detecting coincidence, the storage of the FA on the address line 14 in the SR31-34 is suppressed by a gate 46 and a reading request to the main storage is also suppressed. Consequently, operation can be speeded up. |
