发明名称 DIGITAL PLL CIRCUIT
摘要 PURPOSE:To improve the stability by supplying an output signal of a digital low pass filter via a nonlinear conversion circuit provided with a blind sector for a signal near a prescribed value. CONSTITUTION:The input/output characteristic of a nonlinear conversion circuit 14 is set such that the output is '0' with respect to the input in the range of, e.g. -l-+1. When an input data having a high frequency fluctuation due to peak shift is fed to an input terminal IN, an output of a phase comparator circuit 11 exceeding + or -1 is fed to a digital low pass filter 12. Then an output + or -1 appears at the output of the digital low pass filter 12 depending on its arithmetic error at this point of time. Since the nonlinear conversion circuit 14 has a blind sector of + or -1 as stated above, the output is '0'. Thus, the arithmetic error of the digital low pass filter 12 is absorbed and eliminated by the nonlinear conversion circuit 14, useless fluctuation of a digital PLL circuit 10A is prevented and the stability is improved.
申请公布号 JPS63290410(A) 申请公布日期 1988.11.28
申请号 JP19870125490 申请日期 1987.05.22
申请人 SONY CORP 发明人 SHIMIZUME KAZUTOSHI;KIMURA MUTSUMI
分类号 H03L7/06;G11B20/10 主分类号 H03L7/06
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