| 摘要 |
PURPOSE:To reduce a hard quantity in a master-slave type register, which can hold plural data by using a means to make a master part common to respective fields. CONSTITUTION:A continuous clock is supplied to phi, and the clocks which have the same period of H as phi, and have periods double as log as phi, are supplied to phi1, phi2, by dislocating their phases. Since as for data D1 just before time T1 fetched through a transfer gate TG1 both phi, phi1 go to H, and phi2 go to L at the time T1, the transfer gates TGs 2, 3, 6 become conductive, and the TGs 1, 4, 5 become non-conductive, and a data D1, fetched through a transfer gate TG1, is outputted to an output Q1 through inverters 9, 10. During the time T2, since all phi, phi1, phi2 are L, both a first and a second slave parts come to closed loops, and the values of Q1, Q2 are held. At the time T3, when phi goes to H, phi1 goes to L, and phi2 goes to H, the TGs 2, 4, 5 become conductive, and the TGs 1, 3, 6 become non-conductive. Accordingly, Q1 holds the data D1, and the last data D2 fetched during the T2 period is outputted to the output Q2. At the time T4, the data similar to the T2 is held and hereafter, as for T5-T8, it is a similar operation, excepting that the data are different. |
