Method and arrangement for generating test data for a digital circuit

摘要

In this method, circuit-specific test data are stored in a first memory and are read out in a controlled manner during the test process. To meet the requirements of the special features in bus-oriented circuits, the specific bus protocol required for the testing, which specifies the time-correlation of the test data with the operating phases, are stored in a further memory (S2) and are in each case logically combined with the current test data during the testing process. The invention is mainly applicable in test devices for digital circuits. <IMAGE>