| 摘要 |
PURPOSE:To contrive to shorten the time by setting a clock delay time until outputted to a scan register connected to an output terminal side of a circuit to be tested, to all the same, and testing plural circuits to be tested, by inputting and outputting serial data once. CONSTITUTION:Between a circuit to be tested 1 and a scan register SR2, a register R of a 1-clock delay is inserted in parallel. That is, a parallel input terminal R1 of the register R and an output terminal 10 of the circuit to be tested 1 are connected, and a parallel output terminal R2 of the register R and a parallel input terminal SR22 of the scan register SR2 are connected. In case when each clock delay time of the circuits to be tested 1, 2 are a 3-clock delay and a 4-clock delay, respectively, when the clock delay time of the register R is delayed by 1 clock, the clock delay time to the scan registers SR2, SR3 of the circuits to be tested 1, 2 becomes all the same as a 4-clock delay. Accordingly, when data inputs to the circuits to be tested 1, 2 are executed simultaneously, a result of response of the circuits to be tested 1, 2 can be inputted simultaneously to the scan registers SR2, SR3.
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