| 摘要 |
PURPOSE:To output a signal subject to phase correction without the need of high frequency operation for a clock output means by selecting a clock signal corresponding to the tendency of the phase shift from plural clock signals. CONSTITUTION:Clock signals phi0-phin whose phase differs from each other are given to a data selector 32. That is, a lead input command signal from a binary phase comparator 21 is given to a terminal U of an up-down counter 31 and a lag input command signal is given to a terminal D, binary count outputs Q0-Qm are given respectively to address input terminals Ao-Am of the data selector 32, which selects any of the clock signals phi0-phin in response to the address input at the terminals A0-Am. The selected clock signal is given to a phase controller 24. Since a clock signal corresponding to the tendency of the phase shift is selected from plural clock signals, a signal subject to phase correction is outputted without the need of high frequency operation for the clock output means.
|
