Clock scheme for VLSI Systems.

摘要

An integrated circuit includes an input clock generator circuit (10) responsive to an external TTL level clock signal (C1) for generating an internal CMOS level system clock signal (C2) for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock generator circuit (16) responsive to either the internal CMOS level system clock signal (C2) or an external CMOS level system clock signal (C3) for generating internal CMOS level phase clock signals (01, 02) for its own use. As a result, the integrated circuit has a higher speed of operation since the propagation delay between the CMOS level system clock signal and internal clock signals has been minimized.