| 摘要 |
PURPOSE:To reduce a through current at the time of input change, by connecting every two P-type and N-type MOS transistors (Tr) in series, adding a pulse with a negative phase on the P-type and N-type (Trs) at an outside, and adding an input signal on the P-type and N-type (Trs) at an inside. CONSTITUTION:When the input signal I11 changes from an L to an H, an inverter 11 outputs the L. A two-NAND 16 changes from the H to the L, and an inverter 12 from the L to the H. Meanwhile, the outputs of a two-NOR 17 and an inverter 13 remain unchanged. When the input signal I11 changes from the L to the H and the PMOS TrQ11 and the NMOS TrQ12 are turned ON simultaneously, the gate of the PMOS TrQ13 goes to the H, which increases channel resistance. When the input signal changes from the H to the L, no level change occur in the two-NAND 16 and the inverter 12, and the two-NOR 17 changes from the L to the H, and the inverter 13 from the H to the L. When the PMOS TrQ11 and the NMOS TrQ12 are turned ON simultaneously, the gate of the NMOS TrQ14 goes to the L, which increases the channel resistance. In such a way, it is possible to prevent the increase of the through current due to the change of the input signal from being generated. |
