| 摘要 |
<p>A finite impulse response sampled data filter is provided with parallel tapped delay lines to one of which scaled input samples are applied and to the other of which non-scaled samples are applied. The scaled and non-scaled signal samples from the parallel tapped delay lines are both made available to weighting circuits. At least one of the weighting circuits is coupled to receive samples from taps of both said tapped delay lines which have been equally delayed. Weighted samples are added to produce the filtered output samples.</p> |
