| 摘要 |
PURPOSE:To perform a mask design for a CMOS circuit efficiently by a method wherein a well mask of a single logic CMOS circuit mask is converted. CONSTITUTION:When a two input NAND is needed for a net information, an N-type well mask 102 is generated through a computer treatment for the formation of a CMOS logic circuit mask of the two input NAND. A potential reference connecting section 112 and a potential reference connecting section 114 are connected with a high potential reference and a low potential reference respectively. When a two input NOR is needed owing to a net information, an N-type well mask 202 is generated through a computer treatment for the formation of a CMOS logic circuit mask of a two NOR. A potential reference connecting section 214 and a potential reference connecting section 212 are connected with a high potential reference and a low potential reference respectively. By these processes, a mask necessary for obtaining the CMOS circuit masks of the two input NAND and the two input NOR is only a common mask except their own N-type well mask, thereby man-hours of a mask design and a register, and a memory capacity can be decreased, and therefore a design can be efficiently performed.
|
