发明名称 PICTURE PROCESSOR
摘要 PURPOSE:To obtain a device of simple constitution by generating a clock whose frequency is K-number of times as high as that of a reference clock and thinning M-number of pulses of this generated clock to drop out (M-N)-number of pulses in accordance with a reduction factor N/M and dividing the frequency by 1/K to obtain a sampling clock. CONSTITUTION:A clock CK2 which is four (frequency division ratio) times as high as a reference clock CK1 is outputted from a clock generating circuit 102. This clock CK2 is divided by 1/3 in a first frequency dividing circuit 103 based on reduction factor N/M=2/3 set by the reduction factor set register 100. One pulse is dropped out from the clock CK2 by a gate circuit 104 to generate a clock CK3. The clock CK3 is divided again by 1/4 in a second frequency dividing circuit 105 to generate a sampling clock CK4. A/D-converted picture data is written in a buffer memory 107 by the sampling clock CK4 to obtain picture data which is reduced to 2/3 in the horizontal direction.
申请公布号 JPS63284684(A) 申请公布日期 1988.11.21
申请号 JP19870119437 申请日期 1987.05.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KODA TOSHIYUKI;SHIMEKI TAIJI;TATSUMI TOSHIICHI;KAWAHARA TOSHIYUKI
分类号 G06T3/40 主分类号 G06T3/40
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