发明名称 PRODUCTION OF THIN FILM TRANSISTOR ARRAY
摘要 <p>PURPOSE:To form good electrical connections without eaves and to improve the yield of a transistor array by subjecting two-layered films consisting of SiO2 and Si3N4 films to RIE by using CF4 and O2. CONSTITUTION:ITO layers 1 are selectively deposited on a glass plate 7 and SiO2 is superposed as a transparent insulating layer 8 over the entire surface. Cr layers 2 for scanning signal lines in common use as gate electrodes are then selectively provided thereto. An Si3N4 9 is thereafter provided over the entire surface by a plasma CVD method. A resist mask 20 is formed on the surface and the substrate is set to a parallel flat plate type RIE device, in which CF4 and O2 are passed to bore apertures 4 in the layers 9, 8. Since the etching rate of SiO2 is lower than the etching rate of Si3N4, the apertures 4 are formed satisfactorily without generating the eaves. The defective connections of Al video signal lines 5 in common use as drains and the ITO 1 and the defective connections of the Al layer 6 in common use as the taking out electrode of the scanning signal lines 2 and the scanning signal lines 2 are decreased and the yield of the transistor array is improved.</p>
申请公布号 JPS63284523(A) 申请公布日期 1988.11.21
申请号 JP19870119439 申请日期 1987.05.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TSUTSU HIROSHI;KAWAMURA TETSUYA;KARASAWA TAKESHI;SHIRAI SHIGENOBU;MIYATA YUTAKA;CHIKAMURA TAKAO;TANNO MASUO;NAKAYAMA ICHIRO;NARUSHIGE YASUSHI
分类号 H01L21/302;G02F1/133;G02F1/136;G02F1/1368;G09F9/30;H01L21/3065;H01L21/336;H01L27/12;H01L29/78;H01L29/786 主分类号 H01L21/302
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