| 摘要 |
PURPOSE:To enable fast operation even when the number of stages of counters increases by employing wired-OR constitution for an input to an initial-stage flip-flop circuit. CONSTITUTION:This counter circuit includes a shift register 1 consisting of (n) flip-flop circuits D-FF and an OR circuit 3 which inputs respective outputs Q of the initial stage - (n-1)th stage of the flip-flop circuits DF1-DFn, and the output of this OR circuit 3 is supplied to the initial-stage flip-flop circuit through a wired OR circuit 4. Thus, the Q output of the shift register is shifted to the right successively in response to '0' significance and the wired-OR constitution is employed for the input to the initial-stage D-FF, so even if the number of the stages of the counters increases, the propagation time from the outputs of the 2nd and succeeding D-FF to the input of the initial stage becomes longer only by one gate. Consequently, the fast operation can be secured.
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