| 摘要 |
PURPOSE:To decrease a chip in area by a method wherein a step is provided between a transistor and an adjacent one and an insulating film is formed on a wall of the step. CONSTITUTION:A P channel transistor, which is composed of an N well 2, a P<+> diffusion layer 3, a gate oxide film 5, and a gate electrode 6, is formed on a protruding section of a P-type silicon selectively provided with a step through a photoetching method as well as an N channel transistor consisting of an N<+> diffusion layer 4, a film 5, and an electrode 6 is built on a recesses section. Moreover, PN separation is performed onto a silicon substrate side face between a P and an N channel transistor forming region through an oxide film 7 200 Angstrom thick for instance, thereby a PN separation region can be dispensed with. By these processes, a chip can be remarkably decreased in area.
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