发明名称 MULTI-PROCESSOR SYSTEM
摘要 PURPOSE:To prevent the generation of delay in critical real time processing by allowing a processor to use a bus connecting between subsystems without waiting the end of bus use based upon another subsystem. CONSTITUTION:When a CPU 11 controls a DRQ control part 4, a 1st subsystem 1 interrupts the input of a new bus using request signal to the CPU 11 after the time determined by subtracting the prescribed time determined longer than the maximum value of continuous bus using time required every output of a using request signal DRQ from a 2nd subsystem 3 from the time used by the 1st subsystem 1 itself to execute critical real time processing. Since the bus 2 is not used by the other 2nd subsystem 3 when the 1st subsystem 1 uses the bus 2 in order to execute the critical real time processing, the 1st subsystem 1 can execute the critical real time processing without waiting the end of the bus use based upon the other subsystem.
申请公布号 JPS63282871(A) 申请公布日期 1988.11.18
申请号 JP19870117025 申请日期 1987.05.15
申请人 FANUC LTD 发明人 YONEKURA MIKIO
分类号 G06F13/28;G06F13/36;G06F15/16;G06F15/173 主分类号 G06F13/28
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