发明名称 MULTIPLIER
摘要 PURPOSE:To reduce the number of operation cycles and to rapidly execute multiplication by scanning a multiplier, adding a multiplicand to a partial product only a digit having '1' and collectively shifting a multiplicant by means of a barrel shifter for digits having continuous '0's. CONSTITUTION:Assuming least significant bit out of a multiplier B stored in a multiplier register 2 is Bk (Bk=1, 0<=k<=n-1), '1' is inputted to the k-th digit from the vertical lest significant digit of the barrel shifter 4 from the multiplier B through a control signal circuit 5. The output of multiplicand A stored in a multiplicand register 1 is shifted to the left by (k) bits by means of the barrel shifter 4, the shifted value is added to the contents of a partial product register 3 by an adder 6 and the added result is sent and stored to/in a partial product register 3. The, the bit Bk stored in the register 2 is reset to '0' by a control signal 10. Consequently, the product Y of 2n bits to be the multiplied result is obtained in the register 3 only by repeating the operating number of times corresponding to the number of '1' in the multiplier.
申请公布号 JPS63282839(A) 申请公布日期 1988.11.18
申请号 JP19870118465 申请日期 1987.05.14
申请人 NEC CORP 发明人 KOIKE JUN
分类号 G06F7/53;G06F7/52;G06F7/527 主分类号 G06F7/53
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