| 摘要 |
PURPOSE:To easily confirm the normality of the action of a buffer memory before the manufacturing step and shipment of a bus interface unit, etc., and to classify a test area and an operating area with a processor during the system operation by attaining the access to all areas of the buffer memory from a microprocessor. CONSTITUTION:By a micro-processor 2(2-1, 2-2), a test mode and a writing signal W are generated and an MPU address is selected to a selector 51 by a selecting signal. Next, the address of an area 41 tested by a buffer memory 4(4-1, 4-2) is sent from the processor 2. A decoder 52 decodes the output of the selector 51 and successively enables a chip selecting element CS of the area 41 of the memory 4. The writing signal W is given through an AND gate 21 to the area 41 of the memory 4, the writing data from the processor 2 are written through a data bus 23 to the area 14 of the memory 4, next, the processor 2 turns off the signal W, a reading signal is generated and the area 41 of the memory 4 is read.
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