| 摘要 |
PURPOSE:To generate erroneous data to any transfer data without fail and to efficiently execute the detailed test by converting normal data on a common bus to arbitrary erroneous data with an error generating pattern and supplying them to a fault detecting circuit. CONSTITUTION:To a register 33 of an erroneous data generating circuit 3 through a common bus 1, an error generating pattern is set, and to respective plural bit lines B0-Bn to constitute the bus 1, plural signal inverting elements 320-32n are connected. To the output of the bit lines B0-Bn and the elements 320-32n, selectors 310-31n of two inputs are connected, and the connection at the section of the output of the elements 320-32n to the fault detecting circuit 4 is switched by an error generating pattern. To a register 33, an error generating pattern is set, a signal TP for a test is sent to a microprocessor 8, the output from the circuit 4 is processed by a logic element 5, an error display FF6 and a logic element 7, added to a processor 8 and a parity error is processed by the processor 8.
|
