| 摘要 |
PURPOSE:To obtain a frequency-doubled clock signal with good frequency stability through simple constitution by connecting in-phase outputs of the 1st and the 2nd gate circuits to an input terminal of the 1st AND gate circuit and their antiphase outputs to an input terminal of the 2nd AND gate circuit. CONSTITUTION:When a reference clock signal 1 is impressed to the 1st gate circuit 9 and a delay circuit 10, the gate circuit generates an in-phase output 2 and an antiphase output 3. On the other hand, the output is passed through the delay circuit 10 and the 2nd gate circuit 11 to generate an in-phase output 4 and an antiphase output 5 which are pi/2 delayed behind the signals 2 and 3. The signals 2 and 4 are impressed to the 1st AND gate 12 and the signals 3 and 5 are impressed to the 2nd AND gate 13; and the outputs of the AND gates 12 and 13 are applied to an OR gate 14 to obtain the clock signal 8 of frequency double as high as that of the input clock signal. |
