| 摘要 |
PURPOSE:To attain the accuracy of speed margin evaluation of an LSI chip by setting a data fetch timing of a flip-flop before and after each output buffer by a prescribed number each at an optional time interval. CONSTITUTION:In conducting speed margin evaluation in the function evaluation test of the LSI chip, a shift register 4 is operated by using non-duplicated biphase clocks phi1, phi2. The timing when flip-flop groups 1a-1c provided to the pre-stage of each output buffer B fetches an input data signal I depends on clocks CK1-CK3, the delay in the CK1-CK3 depends on the period of the non-duplicated biphase clocks phi1, phi2. Thus, the clock signal CK is being deviated, that is the period is reduced to apply speed margin evaluation, then the correct data fetch timing of each flip-flop is recognized. Thus, accurate speed margin is attained.
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